HLDVT 2012 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

The seventeenth annual workshop HLDVT 2012 aims to bring together a community of researchers in the areas of design, validation, and test. The workshop addresses the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum for researchers and practitioners to discuss the practical issues associated with validation of extremely large designs.

The topics of interest include (but not limited to):

Simulation-Based Validation
Formal Verification and Hybrid Methods
Design Abstraction & Behavioral Modeling
Error Trace Interpretation and Debugging
On-Chip and Core-Based Testing
Test Generation for Defects, Design Errors, and Delay
Hardware/Software and Mixed-signal System Co-Validation
Emulation and Prototyping
Post-silicon Validation and Debug

Key Dates

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Hotel Reservation deadline: October 26, 2012 (extended)
Advance Registration deadline: October 31, 2012 (extended)

The Venue

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Hyatt Resort and Spa, Huntington Beach
Reservations
Phone: 1-800-872-3600
Online: https://resweb.passkey.com/Resweb.do?mode=welcome_ei_new&eventID=9893904

Workshop Registration

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HLDVT'12 Conference Registration includes a CD-ROM of the proceedings, and the banquet dinner on Friday, November 9, 2012. If you would like to bring a guest to the banquet dinner a guest banquet ticket may be added to your registration.

Register NOW

Advance Program

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Friday -- Saturday

November 9, 2012 (Friday)

7:30 AM - 8:30 AM REGISTRATION & BREAKFAST

8:15 AM - 8:30 AM	OPENING REMARKS

8:30 AM - 10:00 AM	Session 1 - Formal Methods
	Sequential Equivalence Checking of Hard Instances with Targeted Inductive Invariants and Efficient Filtering Strategies Huy Nguyen and Michael Hsiao (Virginia Tech)
	Behavior Driven Development for Circuit Design and Verification Melanie Diepenbeck, Mathias Soeken, Daniel Große and Rolf Drechsler (Univ. of Bremen)
	Using Decision Diagrams to Compactly Represent the State Space for Explicit Model Checking Hao Zheng, Andrew Price (Univ. of South Florida) and Chris Myers (Univ. of Utah)

10:00 AM - 10:30 PM COFFEE BREAK

10:30 AM - 12:00 PM	Session 2 - System-level Modeling
	Automatic Generation of Deadlock Detection Algorithms for a Family of Microarchitecture Description Languages of Communication Fabrics Freek Verbeek (Radboud University Nijmegen) and Julien Schmaltz (Open University of the Netherlands)
	Automatic Generation of Verilog Bus Transactors from Natural Language Protocol Specifications Ian Harris (Univ. of California, Irvine)
	Single-Source Hardware Modeling of Different Abstraction Levels with State Charts Rainer Findenig (FH Hagenberg), Thomas Leitner (DMCE GmbH & Co KG) and Wolfgang Ecker (Infineon Technologies)

12:00 PM - 1:30 PM LUNCH

1:30 PM - 3:30 PM	Session 3 - Assertions, Coverage & Tests
	Using Haloes in Mixed-Signal Assertion Based Verification Dogan Ulus and Alper Sen (Bogazici University)
	A Formal Method to Improve SystemVerilog Functional Coverage An-Che Cheng (National Chiao Tung University), Chia-Chih Yen (Springsoft Inc.) and Jing-Yang Jou (National Chiao Tung University)
	A Functional Test Generation Technique for RTL Datapaths Bijan Alizadeh (Univ. of Tehran) and Masahiro Fujita (Univ. of Tokyo)
	Constrained Signal Selection for Post-Silicon Validation Kanad Basu, Prabhat Mishra (Univ. of Florida) and Priyadarsan Patra (Intel)

3:30 PM - 4:00 PM BREAK

4:00 PM - 5:30 PM	Session 4 - Embedded System and Software Verification
	The Strange Pair: IP-XACT and UNIVERCM to Integrate Heterogeneous Embedded Systems Graziano Pravadelli, Sara Vinco, Franco Fummi and Diego Braga (Univ. of Verona)
	Monitoring Distributed Reactive Systems Yu Bai, Jens Brandt and Klaus Schneider (University of Kaiserslautern)
	Embedded System Verification through Constraint-Based Scheduling (Short Paper) Olfat El-Mahi, Giovanni Beltrame, Gabriela Nicolescu and Gilles Pesant (Ecole Polytechinque de Montreal)
	Accurate profiling of oracles for self-checking time-constrained embedded software (Short Paper) Simone Bronuzzi, Giuseppe Di Guglielmo, Franco Fummi and Graziano Pravadelli (Univ. of Verona)

6:00 PM - 8:00 PM	DINNER
	Validation Challenges in Mobile Computing Upendra Kulkarni, VP of Graphics Software Engineering, Intel

November 10, 2012 (Saturday)

8:30 AM - 10:00 AM	Session 5 - Special Session
	Post-Silicon Validation and Debug Organizer: Prabhat Mishra (University of Florida)
	Post-Silicon Verification and Debugging with Control Flow Traces and Patchable Hardware Masahiro Fujita (University of Tokyo, Japan)
	On-Chip Stimuli Generation for Post-Silicon Validation Nicola Nicolici (McMaster University, Canada)
	Emulation in Post-Silicon Validation: It’s Not Just for Functionality Anymore Kyle Balston, Steve Wilton, Alan Hu (University of British Columbia, Canada)Amir Nahir (IBM Haifa, Israel)

10:00 AM - 10:30 PM COFFEE BREAK

10:30 AM - 12:00 PM	Session 6 - Special Session
	High Speed Discrete Event Simulation Organizer: Samar Abdi, Concordia University
	Eliminating Race Conditions in System-Level Models by using Parallel Simulation Infrastructure Weiwei Chen, Che-Wei Chang, Xu Han and Rainer Doemer (Univ. of California, Irvine)
	Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid (RWTH Aachen University)
	Accelerating SystemC Simulations using GPUs Mahesh Nanjundappa, and Sandeep K. Shukla (Virginia Tech) Anirudh M. Kaushik, Hiren D. Patel (Univ. of Waterloo)

8:30 AM - 12:00 PM	Session 7 - Tutorial (Parallel Session)
	Automatic Formal Verification of Pipelined, Superscalar, and VLIW Processors Miroslav Velev (Aries Design Automation)

12:00 PM - 1:30 PM LUNCH

1:30 PM - 3:00 PM	Session 8 - Special Session
	Toolchain and Simulation Environment for Next Generation Multicore Heterogeneous Platforms: The ToucHMore Approach Organizer: Andrea Acquaviva, (Politecnico di Torino)
	A flexible modeling environment for a NoC-based multicore architecture Romain Lemaire, Sebastien Thuries, Frederic Heiztmann, Claude Helmstetter, Pascal Vivet and Fabien Clermidy (CEA, LETI, France)
	ToucHMore Toolchain and System Software for Energy and Variability Customization Neil Audsley and Ian Gray (University of York, UK), Ralph Haines (ATEGO, UK), Andrea Acquaviva (Politecnico di Torino, Italy)
	Energy aware TLM platform simulation via RTL abstraction Valerio Guarnieri, Nicola Bombieri, Franco Fummi (University of Verona), Andrea Acquaviva (Politecnico di Torino)

3:00 PM - 3:30 PM BREAK

3:30 PM - 5:00 PM	Session 9 - Embedded Tutorial
	Generating Formal System Models from Natural Language Descriptions Rolf Drechsler (Univ. of Bremen), Ian Harris (Univ. of California, Irvine), Robert Wille ((Univ. of Bremen)

5:00 PM - 5:10 PM	Closing Remarks

More Information

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Prab Varma, HLDVT 2012 General Chair

Jackie Horn, Registration Coordinator, HLDVT 2012

Committees

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Organizing Committee

General Chair
Prab Varma, Apache Design

Program Chair
Samar Abdi, Concordia Univ.

Past Chair
Zeljko Zilic, McGill Univ.

Special Sessions Chair
Franco Fummi, Univ. di Verona

New Topics Chair
Sandeep Shukla, Virginia Tech

Finance Chair
Shireesh Verma, Intel

Tutorials Chair
Chinna Prudvi, Intel

Publications Chair
Marc Boul¥e, ¥Ecole de Tech. Sup¥erieure

Web Publicity Co-chairs
Ismet Bayraktaroglu, Sun
Hiren Patel, Univ. of Waterloo

Member-at-Large
Prabhat Mishra, Univ. Florida

Program Committee

Giovanni Beltrame, Poly Montreal
Jens Brandt, Univ. Kaiserslautern
Ed Cerny, Synopsys
Tim Cheng, UC Santa Barbara
Franco Fummi, Univ. di Verona
Ali Habibi, Qualcomm
Ian Harris, UC Irvine
John Hayes, Univ. of Michigan
Michael Hsiao, Virginia Tech
Alan Hu, Univ. British Columbia
Mohamed Jmaiel, ReDCAD, ENIS
Mohammadreza Mousavi, Eindhoven Univ.
Nicola Nicolici, McMaster Univ.
Priyadarsan Patra, Intel
Alper Sen, Bogazici Univ.
Jean-Pierre Talpin, INRIA
Aiguo Xie, Calypto
Miroslav Velev, Aries Design Automation
Lochi Yu, Univ. Costa Rica
Avi Ziv, IBM

Steering Committee

Bernard Courtois, CMP-TIMA
Masahiro Fujita, Univ. of Tokyo
Prab Varma, Apache Design

For more information, visit us on the web at: http://www.hldvt.com/12/

The IEEE International High-Level Design, Validation and Test Workshop (HLDVT 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.